A leadless leadframe package (LLP) is a relatively new integrated circuit package design that contemplates the use of a metal (typically copper) leadframe type substrate structure in the formation of a chip scale package (CSP). As illustrated in FIGS. 1A-1C, in typical leadless leadframe packages, a copper leadframe strip or panel 101 is patterned (typically by stamping or etching) to define a plurality of arrays 103 of chip substrate features. Each chip substrate feature includes a die attach pad 107 and a plurality of contacts 109 disposed about their associated die attach pad 107. Tie bars 111 are used to support the die attach pads 107 and contacts 109.
During assembly, dice are attached to the respective die attach pads and conventional wire bonding is used to electrically couple bond pads (not shown) on each die to their associated contacts 109 on the leadframe strip 101. After the wire bonding, a plastic cap is molded over the top surface of the each array 103 of wire bonded dice. The dice are then singulated and tested using conventional sawing or punching and testing techniques.
FIG. 2 illustrates a typical resulting leadless leadframe package. The die attach pad 107 supports a die 120 which is electrically connected to its associated contacts 109 by bonding wires 122. A plastic cap 125 made of molding material encapsulates the die 120 and bonding wires 122 and fills the gaps between the die attach pad 107 and the contacts 109 thereby serving to hold the contacts in place. It should be appreciated that during singulation, the tie bars 111 are cut and therefore the only materials holding the contacts 109 in place is the molding material. The resulting packaged chip, with the exposed contacts 109 on the bottom of the package, can then be surface mounted on a printed circuit board or other substrate using conventional techniques.
Although leadless leadframe packaging has proven to be a cost effective packaging arrangement, there are continuing efforts to further improve the package structure and associated processing in order to better utilize the space within the resulting devices. Currently, device substrate features often have the same thickness. As such, a die often attaches to a die attach pad that has a same thickness as the surrounding contacts in the device. Therefore, in order to avoid short-circuiting the device, the die size can only be effectively maximized to overhang the die attach pad to the extent of approximately where the inner edge of the contacts is located.
Improved leadless leadframe packaging arrangements and methods that efficiently maximize the die size and easily integrate with current processing techniques are therefore needed.